With recent miniaturization of transistors, the integrity of LSIs is increasing, which leads to an increase in the number of gates and the complexity of logic in LSI designing.
At the time of checking LSI in an LSI designing process, a label (hereinafter, referred to as a “netcode”) is set to a configuration pattern constituted by components, such as, for example, a diode and a transistor, and wirings between terminals of the components to efficiently perform a test. Hereinafter, the “configuration pattern” and the “label” are referred to as a “net” and a “netcode”, respectively.
An overview of an LSI designing process will now be described with reference to a flowchart illustrated in FIG. 1.
First, logic design for performing function verification, such as feasibility study and die-size estimation, is carried out (S101). Physical design, such as creation of a netlist, cell arrangement, and wiring design, is then carried out (S102). After a design rule check, in which whether a designed LSI is compliant with a design rule is checked (S103), an LSI manufacturing process is started (S104).
A detail of the physical designing process illustrated at S102 in FIG. 1 will be described with reference to FIG. 2 next.
In the LSI physical design, a netlist containing information regarding connections between respective terminals of an LSI is created (S110). A layout database containing information regarding components and wirings embedded in the LSI is created (S111). Thereafter, a cell arrangement is designed (S112). Various wirings, such as power wiring, clock wiring, and general wiring, are then designed (S113, S114, and S115, respectively).
Thereafter, a timing check for checking and verifying a variance of LSI internal clock is carried out (S116). Various checks, such as a crosstalk noise check, are then performed (S117).
As described above, a netcode may be set for a net to efficiently perform various check and layout works. In general, a configuration of a target netcode differs depending on various check items.
The netcode has to be correctly set in a short period of time. However, in the related art, netcodes have to be set separately for nets with a user's manual operation, or a tool capable of processing a single net at a time. A complex circuit cannot be handled with such methods. Even if the complex circuit is coped with, the work for setting a netcode for each of hundred-thousands or millions of nets takes considerable time, which may also cause a problem with regard to a time for completion.
In addition, many netcode-setting errors occur. When a wrong netcode is set, the following various check works are not properly carried out, which may result in a problem that an LSI does not correctly work.
Furthermore, a configuration of target nets may differ depending on check items. In such a case, netcodes have to be switched in accordance with the difference in the configuration.